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1 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 high performance 35 40 45 50 max. ras access time, (t rac ) 35 ns 40 ns 45 ns 50 ns max. column address access time, (t caa ) 18 ns 20 ns 22 ns 24 ns min. fast page mode with edo cycle time, (t pc ) 14 ns 15 ns 17 ns 19 ns min. read/write cycle time, (t rc ) 70 ns 75 ns 80 ns 90 ns preliminary v53c8128h ultra-high performance, 128k x 8 bit edo page mode cmos dynamic ram device usage chart operating package outline access time (ns) power temperature temperature range k 35 40 45 50 std. mark 0 c to 70 c ? ? ? ? ? ? blank features n 128k x 8-bit organization n ras access time: 35, 40, 45, 50 ns n edo page mode supports sustained i/o data rates up to 71.5 mhz n low power dissipation ? v53c8128h-50 operating current C 135 ma max ttl standby current C 2.0 ma max n low cmos standby current ? v53c8128h C 1.0 ma max n read-modify-write, ras -only refresh, cas -before- ras refresh capability n refresh interval ? v53c8128h C 512 cycles/8 ms n available in 26/24 pin 300 mil soj package description the v53c8128h is a high speed 131,072 x 8 bit cmos dynamic random access memory. the v53c8128h offers a combination of features: edo page mode for high data bandwidth, fast usable speed, cmos standby current. all inputs and outputs are ttl compatible. input and output capacitances are significantly lowered to allow increased system performance. page mode with extended data out operation allows random access of up to 256 columns (x8) bits within a row with cycle times as short as 14 ns. because of static circuitry, the cas clock is not in the critical timing path. the flow-through column address latches allow address pipelining while relaxing many critical system timing requirements for fast usable speed. these features make the v53c8128h ideally suited for graphics, digital signal processing and high performance peripherals.
2 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 capacitance* t a = 25 c, v cc = 5 v 10%, v ss = 0 v symbol parameter typ. max. unit c in1 address input 3 4 pf c in2 ras , cas , we , oe 45pf c out data input/output 5 7 pf * note: capacitance is sampled and not 100% tested absolute maximum ratings* ambient temperature under bias ............................. C10 c to +80 c storage temperature (plastic) .... C55 c to +125 c voltage relative to v ss .................... C1.0 v to +7.0 v data output current .................................... 50 ma power dissipation ......................................... 1.0 w *note: operation above absolute maximum ratings can adversely affect device reliability. 26/24 lead soj pin configuration top view pin names a 0 Ca 8 address inputs (a 8 : row address only) ras row address strobe cas column address strobe we write enable oe output enable i/o 1 Ci/o 8 data input, output v cc +5v supply v ss 0v supply description pkg. pin count soj k 26/24 family device pkg 3838 01 (t rac ) speed pwr. v53c 128 35 (35 ns) 40 (40 ns) 45 (45 ns) 50 (50 ns) temp. blank (0 c to 70 c) blank (normal) (soj) k h 8 v ss i/o 1 i/o 2 i/o 3 i/o 4 we ras a 0 a 1 a 2 a 3 v cc 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 3838 02 16 15 300 mil v ss i/o 8 i/o 7 i/o 6 i/o 5 cas oe a 8 a 7 a 6 a 5 a 4 14
3 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 block diagram a 0 a 1 a 7 a 8 sense amplifiers refresh counter v cc v ss 9 i/o 1 address buffers and predecoders row decoders 512 memory array column decoders data i/o bus y 0 ? 7 x 0 ? 8 256 x 8 i/o buffer i/o 2 i/o 3 i/o 4 oe clock generator we clock generator cas clock generator ras clock generator oe 3838 03 128k x 8 we cas ras ? ? i/o 5 i/o 6 i/o 7 i/o 8
4 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 dc and operating characteristics (1-2) t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0 v, unless otherwise specified. v53c8128h time min. typ. max. unit test conditions notes i li input leakage current C10 10 m av ss v in v cc (any input pin) i lo output leakage current C10 10 m av ss v out v cc (for high-z state) ras , cas at v ih 35 160 40 150 ma t rc = t rc (min.) 1, 2 45 145 50 135 i cc2 v cc supply current, ras , cas at v ih ttl standby 4 ma other inputs 3 v ss 35 160 i cc3 40 150 ma t rc = t rc (min.) 2 45 145 50 135 i cc4 35 95 40 90 ma minimum cycle 1, 2 45 85 50 80 i cc5 v cc supply current, 2 ma ras =v ih , cas =v il 1 standby, output enabled other inputs 3 v ss i cc6 v cc supply current, ras 3 v cc C 0.2 v, cmos standby 1 ma cas 3 v cc C 0.2 v, all other inputs 3 v ss v il input low voltage C1 0.8 v 3 v ih input high voltage 2.4 v cc +1 v 3 v ol output low voltage 0.4 v i ol = 4.2 ma v oh output high voltage 2.4 v i oh = C5 ma access i cc1 v cc supply current, operating v cc supply current, edo page mode operation v cc supply current, ras -only refresh symbol parameter
5 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 ac characteristics t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0v unless otherwise noted ac test conditions, input pulse levels 0 to 3v 35 40 45 50 # symbol symbol parameter min. max. min. max. min. max. min. max. unit notes 1t rl1rh1 t ras ras pulse width 35 75k 40 75k 45 75k 50 75k ns 2t rl2rl2 t rc read or write cycle time 70 75 80 90 ns 3t rh2rl2 t rp ras precharge time 25 25 25 30 ns 4t rl1ch1 t csh cas hold time 35 40 45 50 ns 5t cl1ch1 t cas cas pulse width 7899ns 6t rl1cl1 t rcd ras to cas delay 16 23 17 28 18 32 19 36 ns 7t wh2cl2 t rcs read command setup time 0000ns4 8t avrl2 t asr row address setup time 0000ns 9t rl1ax t rah row address hold time 6789ns 10 t avcl2 t asc column address setup time 0000ns 11 t cl1ax t cah column address hold time 4567ns 12 t cl1rh1(r) t rsh (r) ras hold time (read cycle) 14 14 15 15 ns 13 t ch2rl2 t crp cas to ras precharge time 5555ns 14 t ch2wx t rch read command hold time 0000ns5 referenced to cas 15 t rh2wx t rrh read command hold time 0000ns5 referenced to ras 16 t oel1rh2 t roh ras hold time 8 8 9 10 ns referenced to oe 17 t gl1qv t oac access time from oe 12 12 13 14 ns 18 t cl1qv t cac access time from cas (edo) 12 12 13 14 ns 6, 7 19 t rl1qv t rac access time from ras 35 40 45 50 ns 6, 8, 9 20 t avqv t caa access time from column 18 20 22 24 ns 6, 7, 10 address 21 t cl1qx t lz cas to low-z output 0000ns16 22 t ch2qz t hz output buffer turn-off delay time 0 6 0 6 0 7 0 8 ns 16 23 t rl1ax t ar column address hold time 28 30 35 40 ns from ras 24 t rl1av t rad ras to column address 11 17 12 20 13 23 14 26 ns 11 delay time 25 t cl1rh1(w) t rsh (w) ras or cas hold time 12 12 13 14 ns in write cycle 26 t wl1ch1 t cwl write command to cas 12 12 13 14 ns lead time jedec
6 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 27 t wl1cl2 t wcs write command setup time 0000ns 12, 13 28 t cl1wh1 t wch write command hold time 5567ns 29 t wl1wh1 t wp write pulse width 5567ns 30 t rl1wh1 t wcr write command hold time 28 30 35 40 ns from ras 31 t wl1rh1 t rwl write command to ras 12 12 13 14 ns lead time 32 t dvwl2 t ds data in setup time 0000ns14 33 t wl1dx t dh data in hold time 4567ns14 34 t wl1gl2 t woh write to oe hold time 5678ns14 35 t gh2dx t oed oe to data delay time 5678ns14 36 t rl2rl2 t rwc read-modify-write 105 110 115 130 ns (rmw) cycle time 37 t rl1rh1 t rrw read-modify-write cycle 70 75 80 87 ns (rmw) ras pulse width 38 t cl1wl2 t cwd cas to we delay 28 30 32 34 ns 12 39 t rl1wl2 t rwd ras to we delay in 54 58 62 68 ns 12 read-modify-write cycle 40 t cl1ch1 t crw cas pulse width (rmw) 46 48 50 52 ns 41 t avwl2 t awd col. address to we delay 35 38 41 42 ns 12 42 t cl2cl2 t pc edo page mode 14 15 17 19 ns read or write cycle time 43 t ch2cl2 t cp cas precharge time 4567ns 44 t avrh1 t car column address to ras 18 20 22 24 ns setup time 45 t ch2qv t cap access time from 21 23 25 27 ns 7 column precharge 46 t rl1dx t dhr data in hold time 28 30 35 40 ns referenced to ras 47 t cl1rl2 t csr cas setup time 10 10 10 10 ns cas -before- ras refresh 48 t rh2cl2 t rpc ras to cas precharge time 0000ns 49 t rl1ch1 t chr cas hold time 8 8 10 12 ns cas -before- ras refresh 50 t cl2cl2 t pcm edo page mode read- 58 60 65 70 ns (rmw) modify-write cycle time ac characteristics (continued) 35 40 45 50 # symbol symbol parameter min. max. min. max. min. max. min. max. unit notes jedec
7 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 ac characteristics (continued) 35 40 45 50 # symbol symbol parameter min. max. min. max. min. max. min. max. unit notes jedec 51 t t t t transition time (rise and fall) 3 50 3 50 3 50 3 50 ns 15 52 t ref refresh interval (512 cycles) 8888ms 53 t coh output hold after cas low 5555ns
8 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 notes: 1. i cc is dependent on output loading when the device output is selected. specified i cc (max.) is measured with the output open. 2. i cc is dependent upon the number of address transitions. specified i dd (max.) is measured with a maximum of two transitions per address cycle in edo page mode. 3. specified v il (min.) is steady state operating. during transitions, v il (min.) may undershoot to C1.0 v for a period not to exceed 20 ns. all ac parameters are measured with v il (min.) 3 v ss and v ih (max.) v dd . 4. t rcd (max.) is specified for reference only. operation within t rcd (max.) limits insures that t rac (max.) and t caa (max.) can be met. if t rcd is greater than the specified t rcd (max.), the access time is controlled by t caa and t cac . 5. either t rrh or t rch must be satisified for a read cycle to occur. 6. measured with a load equivalent to two ttl inputs and 50 pf. 7. access time is determined by the longest of t caa , t cac and t cap . 8. assumes that t rad t rad (max.). if t rad is greater than t rad (max.), t rac will increase by the amount that t rad exceeds t rad (max.). 9. assumes that t rcd t rcd (max.). if t rcd is greater than t rcd (max.), t rac will increase by the amount that t rcd exceeds t rcd (max.). 10. assumes that t rad 3 t rad (max.). 11. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, the access time is controlled by t caa and t cac . 12. t wcs , t rwd , t awd and t cwd are not restrictive operating parameters. 13. t wcs (min.) must be satisfied in an early write cycle. 14. t ds and t dh are referenced to the latter occurrence of cas or we . 15. t t is measured between v ih (min.) and v il (max.). ac-measurements assume t t = 3 ns. 16. assumes a three-state test load (5 pf and a 380 ohm thevenin equivalent). 17. an initial 200 m s pause and 8 ras -containing cycles are required when exiting an extended period of bias without clocks. an extended period of time without clocks is defined as one that exceeds the specified refresh interval.
9 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 waveforms of read cycle waveforms of early write cycle ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (w)(25) t cas (5) t rcd (6) t crp (13) t cah (11) t t rad (24) t wsr t rwh t rah (9) t asr (8) t t wcr (30) t rwl (31) t dh (33) t dhr (46) ih v il v ih v il v ih v il v 2736 06 t t cwl (26) wch (28) t t ds (32) column address valid data-in high-z ras cas we oe i/o address t car (44) asc (10) wcs (27) wp (29) row address ih v il v ras ih v il v cas ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (r)(12) t cas (5) t rcd (6) t crp (13) t cah (11) t asc (10) t rad (24) t rah (9) t asr (8) t rcs (7) t rch (14) t rrh (15) t car (44) t caa (20) t cac (18) t t hz (22) t hz (22) t lz (21) ih v il v we oh v ol v i/o 2736 05 valid data-out address rac (19) column address row address t oac (17) t hz (22) ih v il v oe t roh (16)
10 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 waveforms of oe-controlled write cycle waveforms of read-modify-write cycle ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t rcd (6) t crp (13) t cah (11) t asc (10) t rah (9) t asr (8) row address column address t woh (34) t dh (33) t oed (35) ih v il v ih v il v ih v il v 2736 07 valid data-in t ds (32) t rad (24) ras cas we oe i/o t csh (4) address t car (44) t t cas (5) rsh (w)(12) t wp (29) rwl (31) t cwl (26) t column address v v ih v il v ih v il v t rp (3) t crp (13) t rcd (6) t crp (13) t cah (11) t asc (10) t rah (9) t asr (8) wp (29) rwl (31) t oed (35) t ih v il v ih v il v ih v il v 2736 08 valid data-out t rac (19) t cwl (26) t t rad (24) t t oac (17) t t dh (33) t ds (32) hz (22) cac (18) t lz (21) valid data-in ih v il v oh ol ras cas we oe i/o address t rwc (36) t rrw (37) t ar (23) t csh (4) t rsh (w)(25) t crw (40) t rwd (39) cwd (38) t awd (41) t t caa (20) t rcs (17) row address
11 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 waveforms of edo page mode read cycle valid data out valid data out column address cac (18) t hz (22) t lz hz (22) hz (22) row address column address ih v il v ih v il v rp (3) t ih v il v ih v il v oh v ol v t rah (9) t asr (8) t rcs (7) t rch (14) t csh (4) 2736 09 ih v il v cp (43) t asc (10) rcd (6) t t ras (1) t rsh (r)(12) t cas (5) t cah (11) t t ar (23) t cas (5) t cas (5) pc (42) t crp (13) t t column address t t car (44) t cah (11) t rcs (7) t rcs (7) t rch (14) t oac (17) t t oac (17) t caa (20) t rrh (15) lz (21) t rac (19) t t cac (18) valid data out t crp (13) t t ras cas we oe i/o address t asc (10) t coh cac (18) t hz (22) t caa (20) cap (45) t cah (11) row add ih v il v ih v il v ih v il v ih v il v t t asr (8) 2736 10 ih v il v cp (43) t asc (10) rcd (6) t rsh (w)(25) column address t cah (11) t cas (5) t cas (5) t car (44) t rad (24) t cwl (26) valid data in t crp (13) t wcs (27) wp (29) t cah (11) t asc (10) t cah (11) t dh (33) t ds (32) ih v il v column address rah (9) column address t crp (13) t t wch (28) t cwl (26) t wcs (27) wp (29) t wch (28) t t cwl (26) t wcs (27) wp (29) t wch (28) t valid data in t dh (33) t ds (32) valid data in t dh (33) t ds (32) t rp (3) t ar (23) ras cas we oe i/o address open open t rwl (31) t t csh (4) t ras (1) t pc (42) t t cas (5) waveforms of edo page mode write cycle
12 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 waveforms of ras-only refresh cycle waveforms of edo page mode read-write cycle ih v il v ras ih v il v rp (3) t ih v il v cas t ras (1) t rc (2) t crp (13) t asr (8) t rah (9) 2736 12 we, oe = don? care note: address row add row add ih v il v ih v il v rp (3) t ih v il v i/oh v i/ol v t t asr (8) column address 2736 11 ih v il v cp (43) t asc (10) rcd (6) t t ras (1) t rsh (w)(25) column address t cah (11) t cas (5) t cas (5) t t t crp (13) t rcs (7) t cah (11) t asc (10) t t cwd (38) t lz (21) ih v il v column address t asc (10) rah (9) t wp (29) t cwl (26) t t cwl (26) t rwl (31) t awd (41) t caa (20) t t oac (17) t awd (41) t oac (17) in t cac (18) t oed (35) t ds (32) t dh (33) t lz in out hz (22) t oed (35) ds (32) t dh (33) t t cap (43) t t cac (18) t caa (20) lz in hz (22) t oed (35) ds (32) t dh (33) t t t cac (18) t caa (20) cap (43) t t wp (29) t t wp (29) t cwl (26) t car (44) t rad (24) ras cas we oe i/o address t awd (41) out rac (19) t oac (17) t rwd (39) cah (11) pcm (50) t t csh (4) t cas (5) t cwd (38) hz (22) cwd (38) out t wsr t ems t emh
13 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 i/o ih v il v ras oh v ol v ih v il v cas t ras (1) t rc (2) t cp (43) t hz (22) t csr (47) 2736 14 rp (3) t t rpc (48) t chr (49) rp (3) t we, oe, = don? care note: a ? 0 7 waveforms of cas-before-ras refresh counter test cycle waveforms of cas-before-ras refresh cycle 8 ih v il v ih v il v rp (3) t ih v il v t csr (47) t rsh (w)(25) 2736 13 t ras (1) t chr (49) t rcs (7) t wcs (27) t lz (21) ih v il v ih v il v ih v il v t cp (43) t cas (5) t rch (14) t rrh (15) t roh (16) t oac (17) t hz (22) t hz (22) t hz (22) t rwl (31) t cwl (26) ih v il v ih v il v ih v il v read cycle write cycle t wch (28) i/o address we we i/o d out ras cas oe oe t dh (33) t ds (32) d in
14 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 waveforms of hidden refresh cycle (read) waveforms of hidden refresh cycle (write) ih v il v oh v ol v rp (3) t ih v il v t asr (8) t crp (13) t rcd (6) t rsh (r)(12) t rcs (7) 2736 15 t chr (49) t rad (24) t asc (10) t t cah (11) row add column address t rrh (15) t oac (17) t lz (21) t hz (22) t hz (22) ih v il v ih v il v ih v il v ras cas we oe i/o address valid data rah (9) t caa (20) t cac (18) t rac (19) t ras (1) rp (3) t t ras (1) t ar (23) t crp (13) t rc (2) t rc (2) t hz (22) ih v il v ih v il v rp (3) t ih v il v t ras (1) t rc (2) t asr (8) t crp (13) rp (3) t t rcd (6) t rsh (12) t wcs (27) 2736 16 t ras (1) t ar (23) t chr (49) t crp (13) t rad (24) t asc (10) t rah (9) t cah (11) row add column address t wch (28) t ds (32) ih v il v ih v il v ih v il v valid data-in t dhr (46) t rc (2) ras cas i/o address t dh (33) we oe
15 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 functional description the v53c8128h is a cmos dynamic ram optimized for high data bandwidth, low power applications. it is functionally similar to a traditional dynamic ram. the v53c8128h reads and writes data by multiplexing an 17-bit address into a 9-bit row and an 8-bit column address. the row address is latched by the row address strobe ( ras ). the column address flows through an internal address buffer and is latched by the column address strobe ( cas ). because access time is primarily dependent on a valid column address rather than the precise time that the cas edge occurs, the delay time from ras to cas has little effect on the access time. memory cycle a memory cycle is initiated by bringing ras low. any memory cycle, once initiated, must not be ended or aborted before the minimum t ras time has expired. this ensures proper device operation and data integrity. a new cycle must not be initiated until the minimum precharge time t rp /t cp has elapsed. read cycle a read cycle is performed by holding the write enable ( we ) signal high during a ras / cas operation. the column address must be held for a minimum specified by t ar . data out becomes valid only when t oac , t rac , t caa and t cac are all satisifed. as a result, the access time is dependent on the timing relationships between these parameters. for example, the access time is limited by t caa when t rac , t cac and t oac are all satisfied. write cycle a write cycle is performed by taking we and cas low during a ras operation. the column address is latched by cas . the write cycle can be we controlled or cas controlled depending on whether we or cas falls later. consequently, the input data must be valid at or before the falling edge of we or cas , whichever occurs last. in the cas - controlled write cycle, when the leading edge of we occurs prior to the cas low transition, the i/o data pins will be in the high-z state at the beginning of the write function. ending the write with ras or cas will maintain the output in the high-z state. in the we controlled write cycle, oe must be in the high state and t oed must be satisfied. refresh cycle to retain data, 512 refresh cycles are required in each 8 ms period. there are two ways to refresh the memory: 1. by clocking each of the 512 row addresses (a 0 through a 8 ) with ras at least once every 8 ms. any read, write, read-modify-write or ras - only cycle refreshes the addressed row. 2. using a cas -before- ras refresh cycle. if cas makes a transition from low to high to low after the previous cycle and before ras falls, cas - before- ras refresh is activated. the v53c8128h uses the output of an internal 9-bit counter as the source of row addresses and ignore external address inputs. cas -before- ras is a refresh-only mode and no data access or device selection is allowed. thus, the output remains in the high-z state during the cycle. a cas -before- ras counter test mode is provided to ensure reliable operation of the internal refresh counter.
16 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 extended data out page mode the v53c8128h offers fast access within a row. unlike ordinary fast page mode dram, the v53c8128h output remains active and valid even after cas goes high and it will stay valid for 5ns after cas changes low. the feature allows the v53c8128h to cas cycle faster than ordinary page mode dram since the cycle time be short as data access time. the outputs are disabled at the thz time after ras and cas are high. the thz time is referenced from rising edge of ras or cas whichever occurs last. in addition, high on oe input and activation of the write- cycle will also disable the outputs. the following equation can be used to calculate the maximum data rate: 256 data rate = t rc + 255 x t pc data output operation the v53c8128h input/output is controlled by oe , cas , we and ras . a ras low transition enables the transfer of data to and from the selected row address in the memory array. a ras high transition disables data transfer and latches the output data if the output is enabled. after a memory cycle is initiated with a ras low transition, a cas low transition or cas low level enables the internal i/o path. a cas high transition or a cas high level disables the i/o path and the output driver if it is enabled. a cas low transition while ras is high has no effect on the i/o data path or on the output drivers. the output drivers, when otherwise enabled, can be disabled by holding oe high. the oe signal has no effect on any data stored in the output latches. a we low level can also disable the output drivers when cas is low. during a write cycle, if we goes low at a time in relationship to cas that would normally cause the outputs to be active, it is necessary to use oe to disable the output drivers prior to the we low transition to allow data in setup time (t ds ) to be satisfied. power-on after application of the v cc supply, an initial pause of 200 m s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a ras clock). eight initialization cycles are required after extended periods of bias without clocks (greater than the refresh interval). during power-on, the v cc current requirement of the v53c8128h is dependent on the input levels of ras and cas . if ras is low during power-on, the device will go into an active cycle and i cc will exhibit current transients. it is recommended that ras and cas track with v cc or be held at a valid v ih during power-on to avoid current surges. table 1. v53c8128h data output operation for various cycle types cycle type i/o state read cycles data from addressed memory cell cas -controlled write high-z cycle (early write) we -controlled write oe controlled. high cycle (late write) oe = high-z i/os read-modify-write data from addressed cycles memory cell fast page mode data from addressed read memory cell fast page mode write high-z cycle (early write) fast page mode read- data from addressed modify-write cycle memory cell ras -only refresh high-z cas -before- ras data remains as in refresh cycle previous cycle cas -only cycles high-z
17 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 package outlines 24-pin 300 mil pdip 26/24-pin 300 mil soj 1.310 max. 0.048/0.065 0.018./0.024 .180 max. 0.005/0.050 .100 typ, .008/.013 0.300/0.330 0.250/0.300 0.320/0.390 0.110/0.140 0.05 typ. 0.018 typ. 0.665/0.698 0.025 min. 0.125/0.135 0.028 typ. 0.332/0.342 0.296/0.304 0.255/0.275 0.082/0.093
18 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997
19 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997
20 mosel-vitelic v53c8128h v53c8128h rev. 1.1 november 1997 worldwide offices the information in this document is subject to change without notice. mosel-vitelic makes no commitment to update or keep current the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel-vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. mosel-vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. ? copyright 1996, vitelic corporation 11/97 printed in u.s.a. mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 011-886-2-545-1213 fax: 011-886-2-545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 011-886-35-783344 fax: 011-886-35-792838 japan rm.302 annex-g higashi-nakano nakano-ku, tokyo 164 phone: 011-81-03-3365-2851 fax: 011-81-03-3365-2836 u.s. sales offices central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 214-690-1402 fax: 214-690-0341 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 310-498-3314 fax: 310-597-2174 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 011-852-665-4883 fax: 011-852-664-7535

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